Primitive TCP/IP stack in hardware with SME

Since FPGA's are very low level and have been difficult to work with, many components that a software programmer takes for granted are not readily available. Most components require a setting up a royalty-based licensing deal, making it difficult to approach for academics and experimental development. As scientific equipment frequently uses a TCP connection we would like to have a option to communicate with an FPGA solution via TCP. While a full TCP implementation is nice, we are interrested in a minimum working solution for a protected network. In a protected network, we can assume that there is virtually no packet loss, guarantee that there are no packet reordering, and that the sending and receiving ends will handle flow control. We can also guarantee that there will only be a single connection. Using these constraints we can provide a working TCP stack with a very low area usage. The implementation should be done with SME and can leverage the onboard support for the Ethernet layer. For a single connection-network we can mostly ignore the IP layer and focus only on the TCP layer.

Tags: sme hardware fpga tcp ip network

Activities: Implement a minimum TCP/IP stack in SME such that it can run on an FPGA

Contact: Kenneth Skovhede <>, Brian Vinter <>

Area: Masters